International Journal on Science and Technology

E-ISSN: 2229-7677   •   Impact Factor: 9.88

A Widely Indexed Open Access Peer Reviewed Multidisciplinary Bi-monthly Scholarly International Journal

Call for Paper Volume 16 Issue 1 January-March 2025 Submit your research before last 3 days of March to publish your research paper in the issue of January-March.
Submit Research Paper Join as a Reviewer

Plagiarism is checked by the leading plagiarism checker TurnItIn

Call for Paper

Volume 16 Issue 1
2025

Submit your research paper

Indexing Partners
Academia Advanced Sciences Index Bielefeld Academic Search Engine CiteSeer DRJI Google Scholar Independent Search Engine & Directory Network ISI (International Scientific Indexing) Issuu Mendeley Research Networks
RefSeek ResearcherId - Thomson Reuters ResearchGate Scirus Scribd Semantic Scholar UTeM - Universiti Teknikal Malaysia Melaka Wiki for Call for Papers WorldCat Zenodo

Low-Power Design Verification in Semiconductor Circuits

Author(s) Niranjana Gurushankar
Country United States
Abstract With the increasing demand for portable and energy-efficient electronic devices, low-power design has become a critical aspect of modern semiconductor circuits. This paper explores the challenges and methodologies for verifying low-power designs, focusing on ensuring correct functionality while minimizing power consumption. We discuss various techniques employed throughout the design flow, from architectural level down to gate-level and post-silicon validation. Key topics include power-aware simulation and analysis, static power analysis, Dynamic power analysis, formal verification for low-power design, power-aware equivalence checking, emerging challenges in low-power verification. This paper aims to provide a comprehensive overview of low-power design verification methodologies and highlight the latest trends and challenges in this rapidly evolving field. It will be a valuable resource for researchers and engineers involved in the design and verification of low-power semiconductor circuits.
Keywords Low-Power Design, Semiconductor Circuits, Design Verification, Power Consumption, Power Management, Static Power Analysis, Dynamic Power Analysis, Clock Gating, Power Gating, Voltage Scaling, Frequency Scaling
Field Physics
Published In Volume 12, Issue 4, October-December 2021
Published On 2021-11-03
Cite This Low-Power Design Verification in Semiconductor Circuits - Niranjana Gurushankar - IJSAT Volume 12, Issue 4, October-December 2021. DOI 10.5281/zenodo.14474047
DOI https://doi.org/10.5281/zenodo.14474047
Short DOI https://doi.org/g8vmms
View / Download PDF File

Share this



CrossRef

CrossRef DOI is assigned to each research paper published in our journal.

IJSAT DOI prefix is
10.71097/IJSAT

Downloads
Research Paper Format Copyright Permission Form and Undertaking Form Cover Page Vol 15 Isu 4Cover Page Vol 15 Isu 3Cover Page Vol 15 Isu 2

All research papers published on this website are licensed under Creative Commons Attribution-ShareAlike 4.0 International License, and all rights belong to their respective authors/researchers.

CC-BY-SA Open Access

About IJSAT
Fees & Payment
Current Issue
Publication Archive 		Submit Research Paper
Track Submission Status
Publication Guidelines
Publication Ethics
Peer Review & Plagiarism 		Join as a Reviewer
Editors & Reviewers
Reviewer Referral Program
Get Reviewer Membership Certi. 		Website/Journal Policies
Usage Policy
Content Policies
Privacy Policy
Contact Us Message on WhatsApp +91-9687-182-185 editor@ijsat.org